In the field of this invention it is known that typically in a digital delay line the signal to be delayed is propagated through a line of inverters and a multiplexer (MUX) to select the location (inverter) at which the signal will be output.
However, this approach has the disadvantage(s) that traditionally a digital delay line with high resolution and long delay occupies a big silicon area of an integrated circuit. In order to build a long digital delay line with small silicon area, the resolution must be decreased. In addition, the signal to be delayed is distorted as more as the delay line becomes longer.
A need therefore exists for an arrangement and method for a digital delay line with infinite delay wherein the abovementioned disadvantage(s) may be alleviated.